A Novel SiC Trench MOSFET Structure with Enhanced Short Circuit Robustness

In this paper, a novel SiC trench MOSFET (TMOS) structure N-implanted TMOS is proposed and compared with previous P-implanted TMOS. Specific on-resistance (R
dson, sp
), breakdown voltage (BV), and maximum electric field in gate oxide (E
ox_max
) were optimized by using numerical simulation. It was found the optimal N-implanted TMOS has a 390V higher breakdown voltage than optimal P-implanted TMOS under similar R
dson, sp
. However, E
ox_max
in N-implanted TMOS is higher than P-implanted TMOS under the same blocking voltage. Further, short circuit (SC) simulations were studied under bus voltage of 400 V/800 V. The peak short circuit current (normalized with current rating @V
ds
= 2 V) and energy dissipations were compared for the two devices with varied designs. Both the peak short circuit current and energy dissipation are lower for the N-implanted TMOS at the same SC pulse width. The N-implanted TMOS device have better short circuit robustness.