AnnikaCore: RISC-V Architecture Processor Design and Implementation for IoT

As the IoT industry continues to boom, the market demand for embedded IoT processors will steadily grow in the future. As a new streamlined instruction set architecture, RISC-V has received a lot of attention since its release, and its concise instruction coding and flexible modular extensions make it ideal for the implementation of embedded IoT processors. In this paper, we design a 3-stage pipelined scalar micro-out-of-order processor based on the RISC-V architecture. The processor is compatible with the RV32IMA instruction set and has been verified by simulation and FPGA prototype to be functionally correct with a Coremark performance of 2.93 Coremark/MHz. We finally implemented it using SMIC 180nm process with a main frequency of 50MHz. The final experimental results show that the core circuit of the processor is 35K gate and the power consumption is 0.20 mW/MHz.