Mixed‐Signal and HV ESD Protection

Electrostatic discharge (ESD) protection design for homogeneous integrated circuits (ICs) of same or similar type is well understood and the design philosophy is rather straightforward. This chapter focuses on mixed‐signal ESD protection design considerations associated with different circuit function blocks on a chip. It discusses more ESD design considerations related to multiple power supply domains on a chip. The chapter focuses on yet another very challenging mixed‐signal ESD protection design problem, which is ESD protection design for high (or higher) voltage (HV) ICs that is very different from ESD protection design for low (lower) voltage (LV) ICs. It is vitally important to excise
Local ESD Protection Optimization
, while having a Global ESD protection picture in mind, when designing whole‐chip ESD protection for mixed‐signal and HV ICs.