A Technology Path for Scaling Embedded FeRAM to 28 nm and Beyond With 2T1C Structure

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(HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130 nm node with 1T1C structure. To scale FeRAM to 28 nm or beyond, a high aspect ratio embedded dynamic random-access memory (eDRAM)-like 3-D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantage of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric (FE) capacitor, and a silicon logic reading transistor. First, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability toward 28 nm or beyond was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 900 nm
²
FE capacitor in 2T1C could significantly reduce energy consumption 6.4–
$9.6\times $
compared to the traditional 1T1C FeRAM with similar cell area at 28 nm. Moreover, the area ratio between the FE capacitor and the read transistor is investigated both experimentally and with SPICE simulation, where adjustment of the pulsing scheme is needed for the maximum sense margin to occur. Finally, the performance at 7 nm is estimated in terms of read/write energy and cell area.