A Novel Encoder Architecture for 8-bit Flash ADC

This paper presents design and implementation of novel encoder architecture for low power 8-bit flash ADC. The proposed encoder architecture uses AND-XOR steering logic which is accompanied by the NOR based ROM array. The NOR based ROM array converts 256-bit thermometer code into 8-bit binary code. The proposed encoder circuit requires less hardware as compared to the reported encoders and therefore works at higher frequency and consumes less power and area. The proposed encoder is implemented successfully in 180nm technology and verified using pre-layout and post-layout simulation results