Analysis of ALD Dielectric Leakage in Bulk GaN MOS Devices

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate dielectric materials in vertical GaN MOSFET devices since they are largely responsible for determination of threshold voltage, gate leakage reduction, and semiconductor/dielectric interface traps. SiO
2
, Al
2
O
3
, and HfO
2
films were deposited by Atomic Layer Deposition (ALD) and subjected to treatments nominally identical to those in a vertical GaN MOSFET fabrication sequence. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Breakdown measurements indicate that ALD Al2O3 is an ideal candidate for a MOSFET gate dielectric, with a breakdown electric field near 7.5 MV/cm with no high temperature annealing required to increase breakdown strength. SiO
2
ALD films treated with a post deposition anneal at 850 °C for 30 minutes show significant reduction in leakage current while maintaining breakdown at 5.5 MV/cm. HfO
2
films show breakdown nominally identical to annealed SiO
2
films, but with significantly higher leakage. Additionally, HfO
2
films show more sensitivity to high temperature annealing suggesting that more research into surface cleans is necessary to improving these films for MOSFET gate applications.