Impacts of Area-Dependent Defects on the Yield and Gate Oxide Reliability of SiC Power MOSFETs

Large area SiC power metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a 150 A-200 A or higher current rating are desired by the fast-growing electric vehicles (EVs) market. However, the reliability and yield of large area MOSFETs are limited by the crystal defects in the epitaxial layers. Yield analyses are applied to defect maps of 6-inch commercial SiC n-type wafers. The results show that the defect density needs to be reduced to lower than 0.2 $\text{cm}^{-2}$ to obtain more than 80% yield for the 200 A SiC power MOSFETs. Defects with significant surface morphology also affect the longterm oxide reliability of the devices. Therefore, time-dependent dielectric breakdown (TDDB) measurements are conducted on commercially available SiC power MOSFETs with different current ratings (different chip areas). Degradation of oxide lifetime prediction and more spread-out oxide failure times are observed for the larger commercial power MOSFETs.