High Bandwidth Multi-Modulus Clock Divider

IC design can be divided into two main broad categories of Analog and Digital. The analog block includes receiver (RX) and transmitter (TX) for data transmission which works on different frequency ranges. The digital block consists of FSM's which has an operating frequency in the range of Mega Hz. It is not easy to design a PLL for each block to provide particular frequency to work. This paper reports a Design of multi-modulus Clock divider which will take the PLL output and give the divided output with respect to the division ratio. The design is for 9GHz wide band Programmable multi-modulus clock divider using latch-based static CMOS logic. Proposed clock divider circuit gives a wide range of frequencies from 2-255. The divider is designed using 45nm CMOS technology at supply voltage of 1V. The design is implemented in Cadence Virtuoso and the results are reported.