FPGA Implementation of 32APSK Demodulator for Digital Video Broadcasting DVB-S2

The second generation digital video broadcasting satellite (DVB-S2) is a digital television broadcast standard, designed as a successor for the popular DVB-S system. DVB-S2 is designed for broadcast services such as standard and High Definition Television (HDTV), interactive services such as internet access, and professional data content distribution. 32APSK (Amplitude Phase Shift Keying) is one of the enhanced modulation schemes included in DVB-S2. Design and development of a novel demodulation scheme for 32APSK on a ZED board with Zynq 7000 FPGA using model based design approach is proposed in this paper.