Performance Analysis and Implementation of SRAM Controller on Altera DE2 Board

This paper presents an experimental implementation of memory controller design for a static random-access memory (SRAM) module mounted as external memory unit in Altera DE2 board, a family of Cyclone IV E. Here, four different types of SRAM controller are designed with their ASMD (Algorithmic State Machine Diagram) chart and their responses are compared in terms of resource utilization, power consumption and timing issues. The comparative analysis states that the purposed design is power efficient and utilizes fewer amounts of logic elements (LE) among three different designs. Before this hardware implementation in Altera FPGA board, an extensive logic simulation has been done using ModelSim SE 10.5 logic simulator. The power analysis has been carried out using the Power Analyzer tool on Quartus Prime 18.1 simulation tool. This paper mainly purposes to establish a better memory controller at high performance, high speed, low power consumption so that it can be used at the high speed requirement devices.