Low-Power Ultradeep-Submicrometer Junctionless Carbon Nanotube Field-Effect Diode

Designers of integrated circuits aim to reduce the bias supply voltage (
${V}_{\text {DD}}$
) of devices to make them suitable for low-power applications. Nanoscale field-effect diodes (FEDs) that have been presented so far have some advantages, such as a larger ON/OFF current (
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
) ratio and smaller energy-delay product (EDP) compared to silicon-on-insulator (SoI)-MOSFETs with the same dimensions. However, nanoscale FEDs have
${V}_{\text {DD}}$
values greater than 1 V, which have to be reduced to make them appropriate for low-power applications. This study proposes a junctionless carbon nanotube FED (JL-CNT-FED) structure in which CNT is used as the source–channel–drain material. To turn on the proposed JL-CNT-FED, drain contact has to be extended over the oxide by 10 nm. Additionally, suitable work functions for the auxiliary and control gates significantly reduce
${V}_{\text {DD}}$
in the proposed JL-CNT-FED. The digital performance in terms of
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
ratio, intrinsic gate delay (
$\tau $
), and EDP of the proposed device are investigated through simulation. The design of JL-CNT-FED with
${V}_{\text {DD}} = {0.5}$
V achieves an excellent
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
ratio compared to FEDs that have been introduced so far. Simulation results show that the values of
${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$
ratio and subthreshold power dissipation (SPD) of the proposed JL-CNT-FED with a channel length of 42 nm are, respectively, 1E3 times larger and 196E3 times smaller than those of a regular JL-FED with the same dimensions. The proposed JL-CNT-FED with
$V_{\text {DD}} = {0.5}$
V can undergo channel length scaling down to 10 nm, so this device can be reasonable for low-power digital applications.