Design ADC with PLL of OIS Controller for Camera Image Sensor and Augmented Reality Applications

This article introduces subsampling pipelined analog – to - digital converter (ADC) with phase-locked loop are successfully art and implemented from tsmc 0.18 μm CMOS processing. The ADC with phase-locked loop presents a power efficient amplifier - sharing organization in which additional switches are promoted to decrease the noise during the two operational amplifier sharing successive stages. The sample – and - hold amplifier free organization with correlated input sampling elements enhances wideband signal sampling while effectively reducing a gain mismatch. This architecture builds in OIS controller for image sensor of higher accuracy camera and augmented reality applications.