ReliaVision: In-circuit transistor reliability investigation using XML-based technology reliability information in PDKs

To verify the reliability of integrated circuits before manufacturing and testing, aging simulations can assess the impact of transistor degradation mechanisms on circuit performance. Although available in design environments, they still appear uncommon in circuit design projects. One major problem, from our experience, is the simulation effort that aggravates the problem of mastering verification. We present ReliaVision, an approach to overcome this issue by enabling an in-circuit investigation of transistor reliability based on transient stress simulations of mission profiles and demonstrate it based on an example. We particularly address the task of providing transistor reliability information in process design kits in a machine readable form by using XML syntax.