A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security

Physically unclonable functions (PUFs) have drawn attention as one of the key security primitives for IoT devices since they can provide unique, random, stable, and unclonable hardware fingerprints, ie. keys, for secure authentication. Numerous PUF designs have been evolved to provide stable keys at a lower cost, ie. with small area. Early SRAM-based PUFs [1, 2] had large area $(\gt9,000{\mathrm {F^{2}/bit}})$ and was unstable with a native BER of 8.3*. Various stabilization techniques were proposed such as temporal majority voting (TMV), burn-in, and dark bit masking, at the cost of large additional peripheral circuits and significant loss of challenge-response-pairs (CRPs). But resulting BER was still very high ($\sim$ 1*) even with 8.6x BER improvement. An inverting logic gate cell-based PUF with high reliability [3] and synthesizable PUF [4] were also proposed but the large area (5,057F²/bit,2,686F²/bit) limited cost efficiency. A 2-T amplifer-based PUF achieved 553-782F²/bit area [5, 6] but the initial version had a high BER due to the lack of a stabilization method [5]. Therefore, in the following work [6], a stabilization method was subsequently proposed and BER could be significantly improved. A leakage-based PUF with a lossless stabilization method called ‘remapping’ was proposed in [7], which allowed stabilization without sacrificing CRPs as required in [1–3, 6]. To further improve cost efficiency, a PUF with a differential NAND structure [8] was proposed with an extremely small area of $20{\mathrm {F^{2}/bit}}$. However, there was no means of stabilization applicable, other than TMV, making it unstable and susceptible to voltage or temperature (V/T) variations. Therefore, in this paper, a current-integrated differential NAND-structured PUF (CI NAND-PUF) is proposed, where stabilization methods other than TMV is made applicable. By applying trimming and remapping, up to 12.8x stability improvement is achieved with extremely cost-efficient PUF with 20F²/bit area, while also significantly reducing peripheral circuit overhead on [8].