Novel Multiple-Layer Stack Capacitor and Its Application in the IRPFA Readout Circuit

In this paper, a kind of four-layer stack capacitor is proposed, which has realized the compatibility with the conventional standard
$0.5~\mu \text{m}$
CMOS technology. The effective capacitance per area of the proposed stack capacitor is about three times larger than that of the mono-layer MOS capacitor. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the presented four-layer stack capacitor has been also established with considering the fringe effect. The results show that the root mean square error of the proposed SPICE model is less than 2%. The model has been applied in the simulation design of the infrared focal plane array readout circuit (IRFPA ROIC) successfully. Based on the improved
$0.5~\mu \text{m}$
CMOS process with four-layer stack capacitor, an IRFPA ROIC with
$640\times 512$
array has been implemented and the dynamic range is improved from 73db to 78dB.