Low Power VLSI Architecture for Data Comparators for Non-Linear Imaging Applications

This paper introduces a novel low power VLSI architecture for data comparators for nonlinear imaging applications. The proposed novel architectural design is performed on the target device XCV1000-6bg560. This data comparator is simulated using the compiler tool Xilinx 7.1. This architecture is compared with other existing data comparators and their corresponding output is compared. It is found that the proposed system exhibits comparatively low power when compared to the other existing data comparators. Hence this model works effectively for low power Non-linear imaging applications as compared to other models.