Edge computing SoC implementation of compressive sensing algorithm for single-pixel cameras

One of the most recent applications of compressive sensing is single-pixel cameras, where an image is generated by a reduced set of measurements. This new type of camera has already been implemented in many ways but always relying on a powerful CPU or GPU to run the reconstruction algorithms, limiting the portability and increasing the power consumption of the entire system. In this work, a well-known compressive sensing algorithm called TVAL3 is implemented in a Xilinx SoC embedded device. This algorithm has been used in multiples works of compressive sensing for single-pixel cameras due to its image reconstruction performance. The used device is a Zynq-7000 SoC that has an ARM CPU and allows hardware acceleration via FPGA. The hardware accelerator allows speed up the most time-consuming part of the algorithms to contrast the retard caused by the low-spec CPU. The proposed FPGA accelerator implementation was compared with the CPU-only version as regards quality reconstruction and speed. The results show a nearly 10x improvement in the consumption time and a no reduction in the quality of the reconstructions. The new implementation can be used to the initial phase of new, more portable, and faster single-pixel cameras.