Time to Digital Sensing for Multilevel RRAM Cells

Memristors offer the possibility of implementing multilevel cells in Resistive RAMs providing high-density non-volatile data storage solutions. However the writing and reading processes when these devices are integrated into a crossbar is a problem that has not yet been fully solved. Process and temperature variations must be carefully handled when designing reliable interface circuits for RRAM cells. In this work we present a time-domain reading circuit for multilevel RRAM cells. The sensing operation is performed based on the well-known RC circuit that generates a pulse whose width depends on the state of the cell, providing excellent results in terms of area, energy per bit and scalability. Temperature and process variations have been analysed in depth to validate the effective number of levels a cell may store to be read accurately.