A Low Cost Compact SiC/Si Hybrid Switch Gate Driver Circuit for Commonly Used Triggering Patterns

The hybrid switch (HyS) configured by paralleling silicon Si-IGBT and silicon carbide SiC-mosfet mosfet (SiC/Si HyS) has been widely investigated because of high efficiency as well as low cost. However, one of the main obstacles in the practical application of HyS is the complicated gate driver circuits. Generally, one HyS requires two driver chips and two driving signals to achieve flexible triggering patterns, which leads to more cost and more control complexity. To solve the problems, in this article, a compact gate driver circuit with one driver chip and one driving signal is proposed for HyS working in all commonly used triggering patterns. The operation principle, mathematical analysis of time delay, maximum switching frequency, and the relationship between delay time and triggering pattern are investigated in detail. The modeling and systematical analysis of the turning off transient process are given to clarify the current overshoot generation mechanism for the first time, which is helpful for the designer to consider the device ratio for the reliable operation of HyS. The merits of the proposed driver circuits are simple structure, low control complexity, and low cost, more importantly, providing more flexibility for realizing the commonly used triggering patterns. The feasibility and effectiveness of the proposed HyS gate driver circuit are evaluated by a 2-kW SiC/Si HyS Buck converter prototype with triggering patterns C, D, E, and F. The gate driver circuit with variable triggering patterns design guideline is outlined in this article, which helps the enterprise to integrate a new generation of driver circuit for HyS to facilitate the application of HyS as three terminals devices.