Investigation of the Hysteresis of the Output Capacitance of MOSFETs

In order to analyze the hysteresis of the output capacitance of field-effect transistors, a technique has been developed that makes it possible to identify and investigate the nature of the hysteresis of the output capacitance of MOSFET transistors when operating at high voltage, as well as to estimate the dynamic losses in the transistor due to the hysteresis of the output capacitance. To determine the hysteresis of the output capacitance of the transistor, the Sawyer-Tower circuit is used, which is usually used to determine the dependence of the polarization on the electric field strength of dielectrics. A test setup has been created and experimental studies have been carried out, demonstrating the presence of a hysteresis in the output capacitance of MOSFET transistors.