A Multi-Polynomial CRC Circuit for 5G Standard Using Parallel Pipelining Architecture

This paper proposed a novel parallel pipelining multi-polynomial CRC circuit for high speed data calculation in 5G wireless communication while remaining efficient hardware resource usage, which can dynamically switch calculation between multiple CRC polynomials. The proposed CRC circuit is designed using VHDL and synthesis results are valided on Altera (Intel) Stratix IV FPGA (EP4SGX230KF40C2).