Silicide-related yield enhancement in a deep submicrometer CMOS process

Electrical bitmapping and physical failure analysis were used to detect a small silicide break within a memory circuit which led to severe yield loss on our 0.20 /spl mu/m CMOS process. A parallel, two-phase approach was used to optimize the titanium silicide formation process and the silicon surface preparation prior to titanium silicide. Several process and mask tooling modifications were implemented as a result of these efforts, which led to added robustness of the silicide process module and dramatic increases in wafer probe yield.