Pseudo Epi, materials cost reduction

Historically Intel has used p/p+ epitaxial wafers for all products for more than 15 years. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen free active area, and superior oxide quality compared to polished non-epi wafers. The epi wafers however are large materials cost contributors. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 25 to 30%. Pseudo epi or hydrogen anneal is expected to save Intel 6% of total 200 mm Si production costs in 2002 for one chipset process line. This savings is expected to increase to equivalent of 13% of 200 mm Si production cost when expanded to a 0.13 /spl mu/m microprocessor process.