An Incremental-ΔΣ ADC With 106-dB DR for Reconfigurable Class-D Audio Amplifiers

This brief presents a hybrid ADC, by combining an incremental converter with a delta-sigma modulator (
$\Delta \Sigma \text{M}$
) to achieve a high-dynamic response, intended for audio applications. The circuit uses a ‘zero + first’-order incremental converter with a 4-b quantizer and a third-order
$\Delta \Sigma \text{M}$
. Combining the two binary outputs generates a 576-kHz 6-bit binary flow for directly driving a class-D amplifier. A 4-bit flash used in the incremental running at 1/16 the clock frequency and a one-shift DEM technique compensate for the capacitive mismatch and cancel its effect for input signals lower than −35 dB
$_{FS}$
. The proposed ADC, fabricated in a 0.18-
$\mu \text{m}$
CMOS process, occupies an active area of 1.2 mm
²
and consumes 7.2 mW with a 1.8-V supply. The circuit achieves an SNR/SNDR/DR of 96.8/94.45/106 dB for a 21-kHz signal bandwidth.