A Time Constant Estimation Method for Block RC Circuits with Application to Power Grid Analysis

Realizable reduction methods for RC network analysis are preferred in practice because of their convenience for integration in SPICE simulators and benefit of automatic passivity preservation. TICER (Time Constant Equilibration Reduction) is a well-known circuit reduction method proposed about twenty years ago, but has limitation in its node-wise implementation. Recently, an improved version by block RC reduction is proposed which is demonstrated with better computation efficiency and flexibility in implementation. However, the multi-dimensional extension requires a time constant estimation method for block RC circuits, which is a problem less well studied in the literature. In this paper we propose a RICE-based moment-matching computation method for this task. According to the working frequency we are interested in, we introduce a block circuit time constant (BCTC) measure. We verify by experiment on power grid networks that by eliminating RC blocks with BCTC less than a threshold, elimination would result in less error in the power grid transient simulation.