A Multiplier-less Transform Architecture with the Diagonal Data Mapping Transpose Memory for The AVS3 Standard

For improving the coding efficiency, the next-generation Audio Video coding Standard (AVS3) has contained several advanced compression tools, including the transformation operations. The new coding tool known as PBT (Position Based Transform) is introduced, which brings great coding gains at the expense of high computational circuit areas. To reduce the area of transform module and realize the high-performance hardware implementation, we propose a multiplier-less transform architecture supporting DCT-II and two additional types used in PBT, named DST-VII and DCT-VIII. Moreover, a transpose memory with unified diagonal data mapping is designed to reduce latency in data accessing. Experimental results demonstrate that the proposed architecture achieves significant advantages both in the area reduction and in the throughput rate improvement for the transform module in AVS3.