An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC

Achieving the necessary high bandwidth with heavy load while maintaining good linearity poses big challenges to the input buffer design. This paper presents a wideband input buffer for a 4 GS/s 14-b time-interleaved (TI) analog-to-digital converter (ADC). This buffer utilizes pseudo-differential push-pull architecture with adaptive bias circuit to realize stable performance and high linearity with relative low power. Designed in 28 nm CMOS technology, post-layout simulation shows that this input buffer achieves 73.1 dB SFDR with -1 dBFS input signal, Nyquist input frequency, 1.6 pF load, power consumption of 123 mW (Differential pair).