A GaN Complementary FET Inverter With Excellent Noise Margins Monolithically Integrated With Power Gate-Injection HEMTs

A GaN complementary field-effect transistor (FET) inverter monolithically integrated with power gate-injection high-electron-mobility transistors (HEMTs) was realized on a Si substrate. The GaN p-channel and n-channel logic devices and power devices were fabricated based on a p-GaN/AlGaN/GaN epi-structure. Through optimization of epi-layer thickness and doping, excellent low-level noise margin (NM
_L
) of 1.47 V and high-level noise margin (NM
_H
) of 0.98 V were achieved at a supply voltage
${V}_{\text {DD}}$
of 3 V at room temperature. A maximum current density (
${I}_{\text {D,max}}$
) of 0.36 mA/mm/220 mA/mm at
${V}_{\text {DS}}$
of −3 V/3 V and a threshold voltage
${V}_{\text {TH}}$
of −2.0 V/+2.3 V were achieved in the p-channel and n-channel FETs, respectively. A propagation delay of an inverter stage
$\tau _{\text {pd}}$
in a ring oscillator was measured to be
$1.67~\mu \text{s}$
. The power gate-injection HEMT has an ON-resistance
${R}_{ \mathrm{\scriptscriptstyle ON}}$
of
$18.7~\Omega \cdot $
mm and a breakdown voltage (BV) of 900 V. These results show the great potential of the developed GaN complementary FET technology in the applications of GaN power modules.