Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input

This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional asynchronous control loop which can eliminate the clock power consumption of synchronous LDO. The dual adjustment mode can not only provide wider loading current, but also can reduce output voltage ripple. Moreover, the proposed AD-LDO only uses one bidirectional asynchronous control loop for two adjustment modes, so it can save area and reduce power consumption. Under the 350mV input voltage and 300mV output voltage, the proposed AD-LDO can provide 2.4mA output current with 99.8% current efficiency and only consume
$5~\mu \text{A}$
quiescent current. Therefore, the proposed LDO is suitable for applications of wearable electronic devices with an ultra-low supply voltage.