A 14b 2GS/s DAC with >87 dB SFDR in 0.18 μm BiCMOS Technology

This paper presents a 14b 2GS/s DAC in 0.18 μm BiCMOS. In order to improve the linearity and dynamic performance of the DAC, SiGe HBTs are adopted in this scheme as the DAC current sources, while the digital circuit is fabricated in CMOS technology for the purpose of reducing power consumption and saving chip area. A R-2R resistor ladder, a two-stage segmented decoding circuit and a special current cell is designed in this paper to overcome shortcomings of SiGe HBT in the DAC. The post simulation results show that the DAC achieves a SFDR of 87dB at Nyquist-rate.