Analysis for the Physical Mechanism of the Abnormal Increase of Idsat in NMOS under HCI

Generally speaking, when NMOS is stressed at I
bmax
, its I
dsat
will decrease due to electrons injecting into the oxide [1]-[2]. However, we found that the I
dsat
under HCI stress at I
bmax
will first increase and then decrease, it is similar to the I
dsat
mentioned in other papers [3]-[4], it decreases first, increases in the middle before finally decreasing. We conducted experiments to find possible root causes, such as LDD concentration change, LDD angle of incidence change, and ambient temperature change. The results show that with the I
dsat
increase, the I
b
also showed an increase, but the I
dlin
decreased. The results also reveal that the more severe the HCI, such as low temperature, lower LDD concentration, and a small LDD angle of incidence, the I
dsat
of NMOS during HCI stress will increase obviously due to more increase in I
b
. So we concluded that the I
b
originated from a junction leakage between drain(n+) and LDD(n-), and it increases with HCI stress, but it will be saturated after a amount of time, when the hot electrons from HC impact continue to be injected into the oxide, it will make the I
dsat
to exhibit a turn-around. Finally, the I
s
V
d
curve keeps the MOSFET characteristics, but its saturated current is much smaller than that of I
d
V
d
, this indirectly confirms that the abnormal increase in I
dsat
is strongly related to I
b
and a lot of hot electrons have injected into the oxide. As for the I
dlin
measured by small V
d
always decreases, the leakage current can be neglected because the reverse bias of the junction is small.