Development of Configurable Static Random Access Memory (SRAM) for Space Applications

Developing configurable electronic devices aimed for use in multiple spacecrafts is economical considering the huge costs incurred when developing reliable, radiation hardened devices for space applications. In this context, developing an SRAM device with configurable size and Single-Event Upsets (SEU) mitigation technique(s) is a good choice for critical and semi-critical on-board electronic systems of a spacecraft. This article presents the design of an SRAM device with dynamically configurable size and SEU mitigation techniques, and fabrication using 180 nm Complementary Metal Oxide Semiconductor (CMOS) non-radiation hardened process technology. Implementation of the SRAM design with memory macros/cuts, and the techniques followed for logic synthesis, place and route design activities for achieving the timing closure and best Quality of Results (QoR) are illustrated. Simulation studies, reliability analysis, and memory refresh time give confidence for using this device in spacecrafts with short and long mission life requirements.