Electromigration and IR Voltage Drop Reduction Technique on DDR Memory Block Using Power Grid Augmentation

As technology scales down to nanometres it severely affects the IR (Voltage) drop. Although checking this problem in the earlier stages can speed up the analysis, not many tools are available to fix this. Recently Redhawk has included a new feature to fix the electromigration (EM) and IR voltage drop and achieve signoff. It significantly reduces the manual effort required to minimize the electromigration and IR (EMIR). In this paper, a double data rate (DDR) memory block is implemented using 14 nm technology, the EM and IR voltage drop are analysed. The proposed design has reduced the IR voltage drop values to less than 2% of the VDD value (0.99 V), and concerning EM variation could converge to around 83%. Typically, the value of the EM violations should be less than 100%. Hotspot reduction has been done by adding the metal strips. Thus, it can be concluded that by adding metal strips, and by providing a stronger power delivery network (PDN), we can mitigate the hotspots and therefore reduce the IR voltage drop and EM violations. The worst violated path in the static run before clearing violations is in the Metal (M1) layer has a value of 28.50 mV, and EM violating path is 192%. The total power consumption is found to be 4.11 W before clearing the static EMIR run violations. The worst violating path for the static run after clearing violations is in the M1 layer has a value of 5.60 mV. The total power consumption is measured to be 1.4 W for the static run after clearing violations and, EM violating path is put down to 83%. After using power grid augmentation (PGA), the total power consumption is reduced to 1.29 W. Therefore, there is an IR voltage drop of 28.5mV before PGA and 5.6mV after PGA. From the existing methodology (double row optimization) we can see an IR voltage drop of 29mV as the worst instance drop.