Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration

In this paper, we conducted a group of evaluations on the SpMV kernel with sequential implementation to investigate cache performance on single-core platforms. We verified a similar pattern inside a suite of sparse matrices covering various domains, which makes cache hit rate extraordinary inspiring in a sequential environment. This implicit regularity drove us to propose a cache space splitting approach, aiming at a better locality in dense vector accessing and utilization of large cache capacity in modern processors. Finally, we explored the design space of cache on Matrix 3000 GPDSP and proposed a group of cache parameters, based on our experimental results.