Low Power High Performance Match Line Design of Content Addressable Memory

Content-Addressable Memory (CAM) performs a parallel search operation by comparing the searching data with all contents stored in memory at a single cycle, instead of finding data with address. The structure of the match line (ML) and the search line (SL) is a major factor in power consumption, and various CAMs for low-power and high-speed matching are being studied. In this paper, a structure of CAM that has no pre-charge, which provides low power and has improved the disadvantages of conventional AND gate-based CAM has been studied. We design the proposed CAM architectures on 65-nm process node with 1.2 V operating voltage. Results show that the proposed design performs 21% faster while consuming 23% less leakage power than a conventional design.