A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers

Implementing complex number Nth root with low-complexity hardware is challenging, especially for high-order Nth roots. Since the most commonly used values of N in Nth root computation are integers from 2 to 10, we propose a hardware-friendly architecture for computing square to tenth root of complex numbers, based on coordinate rotation digital computer (CORDIC). Through expanding the range of convergence, the proposed method can support the input range from 10^-8 to 10⁴ and reach the relative error of 10^-6. Then we propose a pipelined architecture to implement it, utilizing the similarity in the N result solution process to reduce the complexity. The synthesized results confirm that the circuit complexity only increases 0.157% compared to calculating one result of the square root.