Source/Drain Contact Engineering of InGaZnO Channel BEOL Transistor for Low Contact Resistance and Suppressing Channel Shortening Effect

We have demonstrated suppression of channel shortening and reduction of Source/Drain (S/D) parasitic resistance (R
para
) in InGaZnO (IGZO) channel FETs after high temperature annealing by inserting an InAlZnO (IAZO) contact layer (CL) between the S/D electrodes and the IGZO channel. Thanks to high bond dissociation energy of Al with oxygen, a tungsten (W) film covered by IAZO maintained low resistivity after high temperature annealing (>400°C), while a W film covered by IGZO significantly increased its resistivity due to the formation of metal oxide interlayer. IGZO channel FETs with an IAZO-CL showed both improvement of threshold voltage (V
th
) roll-off and reduction of R
para
by ~30%, maintaining high mobility (>15 cm
²
/Vs) even after 420°C annealing in N
2
. The insertion of an IAZO-CL is a promising technique to achieve IGZO channel FET with high thermal stability and high on-current.