Pre-driver Modeling and Jitter Estimation under Power Supply Noise

This paper presents the development of nonlinear dynamic behavioral model of the IO buffer circuits' pre-driver stage. A time delay neural network structure is developed to model the electrical circuit behavior of pre-driver in order to identify the mathematical relationship between the input voltage and output switching timing signals under power supply voltage variation. Therefore, the pre-driver model is combined with the last-stage output buffer model to illustrate the improved accuracy of the proposed modelling for capturing the supply variation induced jitter. For instance, the proposed modeling approach presents jitter peak-to-peak error about 9.84% while IBIS like model presents 88% when compared to reference transistor level model.