Total-dose tolerance of the commercial Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-/spl mu/m CMOS process

MOSFETs fabricated in the commercial Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-/spl mu/m CMOS process were characterized with respect to the effects of total dose irradiation. Gate oxide threshold voltage shifts at 70 krad (Si) for both minimum geometry 0.70 /spl mu/m/0.35 /spl mu/m NMOS and PMOS transistors biased for worst-case shifts were less than 70 mV. Off-state field leakage currents for isolated NMOS transistors were near 1 pA at 50 krad (Si), but became large at 100 krad (Si). The effect of a post-irradiation high temperature anneal was to lower these leakage currents to less than 10 pA. PMOS transistors exhibited less than 10 pA leakage for doses up to 150 krad (Si). Measurements on edgeless annular NMOS transistors showed only minor increases in leakage current with total dose up to 2 Mrad (Si), indicating that the increased leakage observed in standard NMOS transistors is the result of field leakage associated with inversion in the bird's beak region at the transistor/field oxide interface. Measurements on field-oxide transistor test structures biased for worst-case threshold voltage shifts showed the transistors inverted between 25 and 50 krad (Si) for 3.3 V operation. Measurements on ring-oscillators biased dynamically during irradiation showed less than a 10% change in gate delay and in power up to 2 Mrad (Si) total dose, suggesting that for actual digital circuits applications, functionality and performance may be able to be maintained to doses substantially above 50 krad (Si) with the application of hardness-by-design techniques to mitigate field-oxide inversion.