Parameters optimization for pin-Tunnel-FETs

The paper reports simulation studies of the Tunnel Field Effect Transistor (T-FET). After CMOS ultimate technological nodes limitation, co-integration with nano-devices is expected. A representative device is T-FET with lower sub-threshold slope than the ideal slope of any MOSFET - 60mV/dec. Some key constructive data to achieve a minimum sub-threshold slope are: doping concentration in median i-region, high-k dielectrics and dielectric thickness. A successful solution is a nano-wire T-FET with simulated slope of 39mV/dec.