Behaviour of FinFET Inverter’s Effective Capacitances in Low-Voltage Domain

The digital circuit design methodologies used conventionally consider the values of input capacitance (C
in
) and parasitic (C
p
) capacitance of an inverter to be a fixed, unique value for a given input voltage transition ΔV
in
. However, it has been reported that the FinFET inverter capacitances show a strong dependence on the circuit parameters, unlike its planar counterparts. This phenomenon was observed and well understood at nominal voltages and was termed as “Extension Transistor Induces Capacitance Shielding” (ETICS). However, while operating at low supply voltages, it is observed that the FinFET capacitances do not follow ETICS and show a different behaviour. Understanding and modelling the behaviour of FinFET device capacitances over a range of supply voltages is crucial when it comes to standard cell design. The behaviour and physical origin of FinFET inverter capacitances at lower supply voltage nodes is explained in this work.