Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing

The enhanced performance of neuromorphic computing over conventional Von Neumann computing results in high accuracy, energy and area efficient operations. The energy efficient neuromorphic systems process the information in the form of spikes. Neural coding schemes is the critical aspect of neuromorphic computing as it defines the relationship between the input sensory information and the spike train. Inter-spike-interval (ISI) encoding shows the advantages of high information density and energy efficiency over rate encoding. This paper shows the analytical modelling of Inter Spike Interval (ISI) decoding scheme. This decoding scheme uses a CMOS implemented sample and hold circuit for ISI to voltage transformation. The circuit is implemented in the Cadence Virtuoso environment using CMOS 180nm technology for analytical verification of the simulation results. Also, to demonstrate the robustness of the decoder circuit, Monte Carlo simulation is done for mismatch and process variation.