Rapid MOSFET Contact Resistance Extraction From Circuit Using SPICE-Augmented Machine Learning Without Feature Extraction

It is desirable to monitor the degradation of integrated circuits (ICs) or perform their failure analysis through their electrical characteristics [such as the voltage-transfer characteristic (VTC), of an inverter]. Such a method is nondestructive, low-cost, and can be applied to a large number of samples. Machine learning is naturally an excellent tool to perform this task. However, it is very expensive, in terms of time and cost, to generate enough experimental data with well-controlled defects to train a reliable machine. Moreover, IC defect signatures and features are usually embedded in the hyperspace of their electrical characteristics and are difficult to extract. In this article, we propose to use dimensionality reduction to extract the defect signature from the IC electrical characteristics using data generated through simulations. A CMOS inverter is used for demonstration. The drain contact resistances, which can increase due to defect or degradation, of the nMOSFET and pMOSFET in an inverter are extracted using a machine based on autoencoder (AE). The machine is trained using data generated from SPICE simulation. The machine is then tested using experimental data and high accuracy is obtained ( ${R}^{\,2} >0.9$ ). In particular, for the first time, through the analysis of the hidden variables, we demonstrate that the machine has effectively extracted the features automatically which obviates the cumbersome feature extraction process.