FPGA-based Design and Implementation of High-Speed Spatial Adaptive Processing

In this paper, a high-speed FPGA implementation of complex spatial adaptive processing system based on Xilinx System Generator is presented to suppress interference for wireless radios. By adopting Complex Delayed Least Mean Square (CDLMS) structure, 200 million-samples-per-second (Msps) throughput rate can be achieved with a 16-bits input/output data, which enables a wideband interference suppression. Furthermore, the orders of the proposed system can be expanded easily without performance decrement of system delay and throughput rate, and the adaptive step factors can be modified if needed. The experimental results show that it can realize 30dB interference suppression of 10MHz BPSK signal within 10000 iterations (i.e. 50us when clock frequency is 200MHz). Compared with Direct Matrix inversion (DMI), the proposed scheme can achieve almost the same interference suppression capacity at the cost of less calculation complexity, and enables a real-time implementation.