A 1ns-Resolution Load Adaptive Digital Gate Driver IC with Integrated 500ksps ADC for Drive Pattern Selection and Functional Safety Targeting Dependable SiC Application

A fully integrated load adaptive digital gate driver is proposed for high-speed and dependable SiC applications. It breaks the trade-off between surge/ringing and switching loss over a wide load range of $0 \sim 8\mathrm{A}$ by selecting the gate patterns stored in 8ch 1.5 kb LUT. Proposed time resolution expansion technique enhance them by more than 31% and reduce LUT size by 1/12. The integrated 500 ksps SAR ADC with steady sampling and automatic VDD selection schemes senses not only the load current, but also the surge and the short circuit for functional safety