A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N

This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase-locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard reference frequency. The
$4\times $
ROS phase detector (PD) increases the phase-detection rate
$4\times $
in a power-efficient manner in order to reduce the in-band phase noise contributed from the PD. This improves the overall figure of merit (FoM) and locking speed. A class-F
₃
oscillator generates both ~10GHz and its third harmonic. The former is fed to the feedback divider, while the latter is extracted to generate the ~30-GHz output. The fractional phase and reference distortions are compensated in digital with the assistance of DACs. The proposed ROS-ADPLL is implemented in 28-nm CMOS. Using a standard 50-MHz reference frequency, it achieves 237-fs rms jitter while consuming only 11.9mW, reaching best-in-class FoM
_jitter-N
of −269.3dB.