Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultra-high Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.