Active Current Balancing for Paralleled SiC Semiconductors in Time-Staggered Switching Mode

The steep voltage slopes of today’s wide-bandgap (WBG), fast-switching power semiconductors — like SiC and GaN — lead amongst other challenges to reflection on long cables and thereby overvoltage at inductive loads. To enable the use of these inverters with motors without specially reinforced insulation the voltage slopes need to be slowed down. This article presents a new low-loss countermeasure, which involves the parallel connection of two half-bridges via an interphase transformer. For this one half-bridge is delayed relative to the other one by a delay tuned to a resonant circuit. Undesired DC components in the cross-current of the interphase transformer occur due to non-idealities in the voltage symmetry. The subsequent DC magnetization ultimately can cause the core to saturate. The paper describes the effects due to inaccurate timings and the aspects to keep in mind when dimensioning the magnetic core. Also, this article describes an approach to deal with the undesired current components using a closed-loop control. For that, a special differential-mode shunt is used which enables a dedicated measurement of the cross-current mean value and mitigates the influence of the switching frequency. Finally, the controller concept is presented. The controller is implemented and verified on a 500 kVA SiC inverter test bench.