2:1 MUX Design Using Multitudinous Logic Families at 45nm Technology

Ultra-low-power CMOS IC is essential for contemporary biomedical devices and communication systems. The above-mentioned system’s performances is estimated in terms of small power dissipation throughout operations. In CMOS circuits during discharging phase, huge energy is dissipated in the form of heat. Since multiplexer is the principal component of a communication system. So to enlarge the regulation of transmission of data and to change parallel form of data into serial form, a well organized design of mux is essential. Hence I designed 2:1 MUX schematic using static CMOS, Ratioed Logic, TGL, PTL and PTL with pull up to identify which of the logic family is appropriate for the designing of MUX. The execution is finished in VLSI technology. It’s characteristics are low cost, compact size, high operating speed and moderate power.