A Compact Spice Model for SiC Gate Turn-Off Thyristors With Complete Parameter Extraction Procedure

In this article, a compact subcircuit model for silicon carbide (SiC) gate turn-off thyristors (GTOs) is developed in which static (including conduction and blocking) and dynamic characteristics are completely covered for the first time. The proposed model is composed of two improved 2T-3R models in parallel, and the delay between different submodels is represented by capacitance and resistance. The DC voltage source and variable capacitance are added to reflect the conductivity modulation effect in the forward conduction state, and parasitic effects are also considered. A complete extraction procedure is set up to determine all model parameters (including transistor parameters) from calculation and measurement curves. The model is validated by comparing the simulation results of the model with the experimental results of a self-fabricated 4H-SiC GTO, and the results show a high degree of accuracy.